Key Responsibilities – Mask Design Technologist Layout Design & Optimization: Develop and optimize peripheral and core circuit layouts for Analog, Digital, and Mixed-signal domains, ensuring adherence to design specifications, performance requirements, and foundry rules. Design Verification: Perform DRC (Design Rule Check) and LVS (Layout Versus Schematic) verification, parasitic extraction, and sign-off methodologies to guarantee design integrity and first-pass success. Power Distribution & Floorplanning: Analyze and implement full-chip power distribution strategies and floorplanning optimization to ensure efficient electrical performance, minimize parasitics, and reduce die size. Cross-Functional Collaboration: Work closely with design and process engineering teams across multiple sites to resolve issues, align methodologies, and drive project success while maintaining high standards of accuracy and consistency.
Your Experience and Role Expectation Extensive IC Layout Design: Over 15 years of proven expertise in custom full-chip layouts across analog, digital, and mixed-signal domains, with deep understanding of power distribution and signal planning. Tool Proficiency: Highly skilled in industry-standard layout verification tools (DRC/LVS, parasitic extraction, and sign-off methodologies). Floorplanning Expertise: Strong background in floorplanning strategies and placement optimization to minimize parasitics and reduce die size using a correct-by-construction approach. Cross-Functional Collaboration: Adept at working with multi-site, cross-disciplinary teams and managing small teams to drive project success. Communication & Methodology: Strong verbal and written communication skills with knowledge of layout automation techniques and a proactive mindset toward continuous improvement and efficiency.
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