The SoC Development team is seeking a highly motivated Technologist SoC Validation Engineer to join a team of experienced engineers working on the development of advanced controller SoCs. As a SoC Validation Engineer , you will be responsible for planning, architecting, and executing validation strategies to validate complex hardware in System-on-Chip (SoC) ASICs. Your work will enable industry-leading data storage control SoCs deployed into high-volume consumer and enterprise products. The growing diversity of data creates an exponential number of new possibilities – for the world, our company, and you. You’ll be part of a team driving the innovations necessary to outpace new demands and challenges everywhere data lives, from sensors to mobile devices to the cloud. We’ve only started to scratch the surface of what data can do. You can help unlock its full potential. Essential Duties and Responsibilities Ownership: End-to-end ownership of one or more subsystems or SoC validation flows , including planning, execution, and closure. Leadership & Mentorship: Lead and mentor junior/mid-level engineers, review their test plans, debug approaches, and ensure coverage and closure goals are met. Validation Strategy & Sign-Off: Define SoC-level validation strategies, establish sign-off criteria (functional, performance, power, stress, and PVT coverage), and drive execution to closure across multiple teams. Pre-/Post-Silicon Validation: Strong experience in bring-up, including board initialisation, power-on sequences, processor boot, and system debug . Datapath Validation: Ability to understand and validate complex datapath flows of the controller, create datapath scenarios in SoC verification environment and port them across pre-silicon and post-silicon environments . Protocol Expertise: Validation experience with DDR, PCIe, LPDDR, USB, Ethernet, I²C, I3C, SPI, AXI, AHB, APB . Emulation Experience: Run complex SoC validation scenarios on Palladium/Emulation platforms to accelerate debug and pre-silicon coverage. Firmware & HAL Development: Develop firmware, bare-metal tests, and Hardware Abstraction Layer (HAL) to enable datapath, integration, and SoC-level validation. Validation Infrastructure: Build and maintain validation infrastructure, including test content, regression automation, and lab equipment integration (oscilloscopes, analyzers, logic probes). Debug Expertise: Proficiency in debugging SoC issues across multiple domains (digital logic, firmware, timing, low-power, DFT) using JTAG, trace, waveform capture, and performance counters . Power & GLS Validation: Run and debug gate-level simulations, power-aware (UPF/CPF) validation , and validate ATE functional patterns. Performance & Stress Testing: Validate performance bottlenecks, traffic generation, and corner-case stress scenarios at the SoC level.
Required: BE or MS degree in Electrical Engineering or Computer Engineering, with 9–13 years of in SoC pre-/post-silicon validation and bring-up . Deep understanding of C, embedded programming, and hardware/software co-validation methodologies . Good understanding of SoC verification environments, SystemVerilog (SV), and UVM concepts. Proven history of developing and executing validation strategies for complex SoCs. Skills: Team Leadership & Mentorship: Lead a team of validation engineers, review their test plans, debug approaches, and guide them toward coverage and closure goals. Validation Strategy & Sign-Off Ownership: Define SoC-level validation strategies, establish sign-off criteria (functional, performance, power, stress, PVT, etc.), and drive execution to closure across multiple teams. Ability to develop and execute validation plans at IP, subsystem, and SoC levels. Strong experience in pre-/post-silicon bring-up , including board initialization, power-on sequences, and processor boot. Prior experience in validation of DDR and PCIe protocols at both pre- and post-silicon stages. Knowledge of various interfaces and standards : PCIe, LPDDR, USB, Ethernet, I²C, I3C, SPI, etc. Strong understanding of bus protocols (AXI, AHB, APB) and interconnect fabrics. Ability to understand and validate complex datapath flows and system-level interactions in SoCs. Ability to create complex datapath scenarios in SoC verification environments and port them to both pre-silicon and post-silicon validation . Proficiency in ASIC verification simulation tools (simulation, emulation, and debug environments). Emulation Experience: Running simulations and system-level validation on Palladium/Emulation platforms for datapath and SoC scenarios. Firmware Development: Hands-on experience in developing firmware and bare-metal tests to validate datapath scenarios and SoC integration. HAL Development: Experience in Hardware Abstraction Layer (HAL) development to support SoC validation and software bring-up. Experience with validation infrastructure development : test content, regression automation, and lab equipment integration (oscillosc