We are looking for a Front‑End PCIe Firmware Engineer to design, develop, and maintain the device‑side PCIe Front‑End firmware stack for next‑generation high‑performance storage controllers. In this role, you will own key layers of the PCIe firmware responsible for link bring‑up, configuration space management, MMIO, interrupts, DMA, and command/queue handling , working closely with hardware, validation, and host‑software teams. Key Responsibilities PCIe Front‑End Firmware Development Design and implement firmware for PCIe initialization, link bring‑up, and configuration space programming (BARs, capabilities, MSI/MSI‑X). Develop MMIO‑based control and status interfaces used by host software. Work closely with DMA engines to enable high‑bandwidth, low‑latency host‑to‑device and device‑to‑host data transfers. Architecture & Cross‑Functional Collaboration Collaborate with hardware design teams on PCIe IP integration and bring‑up. Partner with validation teams on FPGA, emulation, and ASIC debug. Work with host‑side driver and system software teams to define clean, scalable interfaces. Debugging & Performance Optimization Debug complex system‑level issues spanning firmware, hardware, and host. Profile and optimize PCIe throughput, latency, and interrupt efficiency. Support bring‑up on pre‑silicon and post‑silicon platforms.
Education Bachelor’s or Master’s degree in Computer Engineering or related field. Experience 8+ years of hands‑on experience in firmware or embedded systems development . Strong experience with PCIe protocol fundamentals , including configuration space, BARs, MSI/MSI‑X, and link states. Proven experience in C/C++ firmware development on RTOS or bare‑metal environments. Technical Skills Solid understanding of MMIO, interrupts, DMA, cache coherency, and memory ordering. Experience debugging low‑level issues using JTAG, logic analyzers, firmware traces, or PCIe protocol analyzers. Comfortable working with hardware specifications and silicon bring‑up flows. Experience with storage or accelerator devices (NVMe‑like protocols, custom command interfaces). Exposure to PCIe switch topologies and peer‑to‑peer (P2P) flows. Experience with pre‑silicon validation environments (FPGA, emulation, or virtual platforms). Familiarity with security, reset isolation, or secure boot interactions at the Front‑End.
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